| Server IP : 74.208.127.88 / Your IP : 216.73.216.159 Web Server : Apache/2.4.41 (Ubuntu) System : Linux ubuntu 5.4.0-163-generic #180-Ubuntu SMP Tue Sep 5 13:21:23 UTC 2023 x86_64 User : www-data ( 33) PHP Version : 7.4.3-4ubuntu2.29 Disable Function : pcntl_alarm,pcntl_fork,pcntl_waitpid,pcntl_wait,pcntl_wifexited,pcntl_wifstopped,pcntl_wifsignaled,pcntl_wifcontinued,pcntl_wexitstatus,pcntl_wtermsig,pcntl_wstopsig,pcntl_signal,pcntl_signal_get_handler,pcntl_signal_dispatch,pcntl_get_last_error,pcntl_strerror,pcntl_sigprocmask,pcntl_sigwaitinfo,pcntl_sigtimedwait,pcntl_exec,pcntl_getpriority,pcntl_setpriority,pcntl_async_signals,pcntl_unshare, MySQL : OFF | cURL : ON | WGET : ON | Perl : ON | Python : OFF | Sudo : ON | Pkexec : ON Directory : /proc/self/root/lib/modules/5.4.0-163-generic/build/arch/xtensa/include/asm/ |
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/* * Xtensa MX interrupt distributor * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 - 2013 Tensilica Inc. */ #ifndef _XTENSA_MXREGS_H #define _XTENSA_MXREGS_H /* * RER/WER at, as Read/write external register * at: value * as: address * * Address Value * 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p * 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p * 0180 0...0m..m Clear enable specified by mask (m) * 0184 0...0m..m Set enable specified by mask (m) * 0190 0...0x..x 8-bit IPI partition register * VVVVVVVVPPPPUUUUUUUUUUUUUUUUU * V (10-bit) Release/Version * P ( 4-bit) Number of cores - 1 * U (18-bit) ID * 01a0 i.......i 32-bit ConfigID * 0200 0...0m..m RunStall core 'n' * 0220 c Cache coherency enabled */ #define MIROUT(irq) (0x000 + (irq)) #define MIPICAUSE(cpu) (0x100 + (cpu)) #define MIPISET(cause) (0x140 + (cause)) #define MIENG 0x180 #define MIENGSET 0x184 #define MIASG 0x188 /* Read Global Assert Register */ #define MIASGSET 0x18c /* Set Global Addert Regiter */ #define MIPIPART 0x190 #define SYSCFGID 0x1a0 #define MPSCORE 0x200 #define CCON 0x220 #endif /* _XTENSA_MXREGS_H */